`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    16:33:19 03/31/2014 
// Design Name: 
// Module Name:    user_control 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module user_control(clk, clk_key, data_key, rst, led, HS, VS, red, green, blue
    );
	input clk, clk_key, rst, data_key;
	output [7:0] led;
	output HS, VS;
	output [2:0] red, green;
	output [1:0] blue;
	reg [2:0] status;//[0]bullet, [2:1] direction
	
 
   wire data;
	wire [7:0] key;
   keyboard keyboard(clk_key, data_key, key); 
	
	assign led = key;
	wire left, right, bullet;
	
	assign left = (key  == 8'b01101011)?(right?0:1):0;
	assign right = (key == 8'b01110100)?(left?0:1):0;
	assign bullet= (key == 8'h75)?1:0;
	
	always@(*)
	begin
		status[0] <= bullet;
		status[1] <= left;
		status[2] <= right;
	end
	
	wire [2:0] data_in;
	assign data_in = status;
	
	vga_display(clk, rst, data_in, HS, VS, red, green, blue);

endmodule
